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6 bit 300 / 309 channel tft - lcd source driver november . 1999. ver. 0. 1 prepared by: sangho park mrno1 @samsung.co.kr s 6c 0641 contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 2 S6C0641 specification revision history version content date 0.0 original aug . 1999 0.1 the content of page 21 has been modified nov . 1999
6 bit 300 / 309 channel tft-lcd source driver S6C0641 3 contents introduction ................................ ................................ ................................ ................................ ................. 4 features ................................ ................................ ................................ ................................ ......................... 4 block diagram ................................ ................................ ................................ ................................ .............. 5 pin assingments ................................ ................................ ................................ ................................ ............ 6 pin descriptions ................................ ................................ ................................ ................................ ........... 7 operation description ................................ ................................ ................................ ............................... 8 display data transfer ................................ ................................ ................................ ............................ 8 extension of output ................................ ................................ ................................ ............................... 8 relationship between input data value and output voltage ................................ .................. 9 absolute maximum ratings ................................ ................................ ................................ .................... 18 recommended operation conditions ................................ ................................ ................................ .. 18 dc characteristics ................................ ................................ ................................ ................................ ... 19 ac characteristics ................................ ................................ ................................ ................................ ... 20 waveforms ................................ ................................ ................................ ................................ ................... 21 relationships between clk1, start pulse (dio1, dio2) and blanking period ........................ 22
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 4 introduction the S6C0641 is a 300 channel or 309 channel output, tft - lcd source driver for 64 gray scale displays. data input is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 colors by output of 64 values gamma -corrected. this device has an internal d/a ( d igital-to- a nalog) converter for each output and 9 or 11 external power supplies. S6C0641 can be adopted to larger panel, and shl ( s hift d irection s election) pin makes use of the lcd panel connection conveniently. maximum operation clock frequency is 55 mh z at a 3.3 v logic operation . i t can be applied to the tft - lcd panel of sv ga, xga standards. features tft active matrix lcd source driver lsi 64 gray scale is possible through 9 or 11 external power supply and d/a converter l ine inversion display is possible cmos level input compatible with gamma-correction l ogic supply voltage: 3.0 - 5.5 v lcd driver supply voltage: 3.0 - 5.5 v output dynamic range: 2.6 - 5.1 vp-p maximum operating frequency: fmax = 55 mhz (internal data transmission rate at 3.3 v operation) o utput: 300 / 309 outputs tcp available
6 bit 300 / 309 channel tft-lcd source driver S6C0641 5 block diagram output buffer d/a converter data register 100 / 103 bit shift register data control selt 6 y001 y002 y003 y307 y308 y309 dio2 dio1 clk2 d00 - d05 d10 - d15 d20 - d25 6 6 18 6 6 6 6 6 6 vgma1 - vgma11 11 data latch 6 6 6 6 6 6 clk1 shl testb figure 1. S6C0641 block diagram
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 6 pin assignments y001 y002 y003 y004 y309 y308 y307 y306 S6C0641 (top view) vss2 vdd2 vgma6 d10 d11 d12 d13 d14 d15 d00 d01 d02 d03 d04 d05 d20 d21 d22 d23 d24 d25 dio1 vgma7 vss1 vgma10 vgma2 vgma1 vgma3 vgma4 vgma5 vgma11 vdd1 vdd2 vss2 shl clk2 dio2 clk1 selt vgma9 vgma8 figure 2. S6C0641 pin assignments
6 bit 300 / 309 channel tft-lcd source driver S6C0641 7 pin descriptions symbol pin name description vdd1 logic power supply 3.0- 5.5 v vdd2 driver power supply 3.0 - 5.5 v vss1 logic ground ground (0 v) vss2 driver ground ground (0 v) y1 ? y 309 driver outputs the d/a converted 6 4 gray scale analog voltage is output. d0<0: 5 > - d 2 <0: 5 > display data input the display data is input with a width of 18 bits, gray-scale data ( 6 bits) by 3 dots (r,g,b) dx0: lsb, dx 5 : msb shl shift direction control input this pin controls the direction of shift register in cascade connection. the shift direction of the shift registers is as follows. shl = h: dio1 input, y1 ? y 309 , dio2 output shl = l: dio2 input, y 309 ? y1, dio1 output dio1 start pulse input / output shl = h: used as the start pulse input pin. shl = l: used as the start pulse output pin. dio2 start pulse input / output shl = h: used as the start pulse output pin. shl = l: used as the start pulse input pin. clk2 shift clock input refer to the shift register's shift clock input. the display data is loaded to the data register at the rising edge of clk2. clk1 latch input latches the contents of the data register at rising edge and transfers them to the d/a converter. also, after clk1 input, clears the internal shift register contents. after 1 pulse input on start, operates normally. clk1 input timing refers to the "relationships between clk1 start pulse (dio1, dio2) and blanking period" of the switching characteristic waveform. selt 300 / 309ch output control input this pin controls 300ch or 309ch output. selt = h: 309ch output ? y151 to y159 are useless. selt = l: 300ch output. ? y151 to y159 are useless. this pin is internally pulled-up.(rpu = 30 k w ) vgma1 ? vgma1 1 gamma corrected power supplies input the gamma corrected power supplies from external source. vdd2 3 vgma1 > vgma2 > ??? > vgma 10 > vgma 11 3 vss2 keep gray-scale power supply unchanged during the gray-scale voltage output. test b test input test b = h : normal operation mode test b = l : test mode (op amp cut-off) this pin is internally pulled-up.(rpu = 30 k w )
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 8 operation description display data transfer when dio1 (or dio2) pulse is loaded into internal latch on the rising edge of clk2, dio1 (or dio2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of clk2. once all the data of 300 / 309 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though clk2 is provided until next dio1 (or dio2) input. when next dio1 (or dio2) is provided, new display data is valid on the next rising edge of clk2 after the falling edge of dio1 (or dio2). extension of output output pin can be adjusted to an extended screen by cascade connection. (1) shl = "l" connect dio1 pin of previous stage to the dio2 pin of next stage and all the input pins except dio1 and dio2 are connected together in each device. (2) shl = "h" connect dio2 pin of previous stage to the dio1 pin of next stage and all the input pins except dio2 and dio1 are connected together in each device.
6 bit 300 / 309 channel tft-lcd source driver S6C0641 9 relationship between input data value and output voltage the lcd drive output voltages are determined by the input data and 11 gamma corrected power supplies (vgma1 - vgma11). shl = l output - data shl = h - data output y1 y2 y3 ...... y307 y308 y309 first last d00 - d05 d10 - d15 d20 - d25 ...... d00 - d05 d10 - d15 d20 - d25 y1 y2 y3 ...... y307 y308 y309 last first d00 - d05 d10 - d15 d20 - d25 ...... d00 - d05 d10 - d15 d20 - d25 figure 3. relationship between shift direction and output data vgma1 vgma6 vgma7 vgma8 vgma9 00h 07h 0fh 17h 27h 2fh 37h 3fh vss2 vdd2 vgma10 vgma5 vgma2 vgma3 vgma4 1fh vgma11 figure 4. gamma correction curve
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 10 table 2. relationship between input data and output voltage value: in case of using 11 levels of gamma-corrected power supplies (vgma1 to vgma11) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vh0 vh1 vh2 vh 3 vh4 vh 5 vh 6 vh7 vgma1 vgma 3 + (vgma2 ? vgma 3 ) 6/7 vgma 3 + (vgma2 ? vgma 3 ) 5/7 vgma 3 + (vgma2 ? vgma 3 ) 4/7 vgma 3 + (vgma2 ? vgma 3 ) 3/7 vgma 3 + (vgma2 ? vgma 3 ) 2/7 vgma 3 + (vgma2 ? vgma 3 ) 1/7 vgma 3 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vh 8 vh9 vh 1 0 vh 1 1 vh12 vh 13 vh 1 4 vh15 vgma 4 + (vgma 3 ? vgma 4 ) 7/8 vgma 4 + (vgma 3 ? vgma 4 ) 6/8 vgma 4 + (vgma 3 ? vgma 4 ) 5/8 vgma 4 + (vgma 3 ? vgma 4 ) 4/8 vgma 4 + (vgma 3 ? vgma 4 ) 3/8 vgma 4 + (vgma 3 ? vgma 4 ) 2/8 vgma 4 + (vgma 3 ? vgma 4 ) 1/8 vgma 4 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vh 16 vh17 vh 18 vh 19 vh20 vh2 1 vh2 2 vh23 vgma 5 + (vgma 4 ? vgma 5 ) 7/8 vgma 5 + (vgma 4 ? vgma 5 ) 6/8 vgma 5 + (vgma 4 ? vgma 5 ) 5/8 vgma 5 + (vgma 4 ? vgma 5 ) 4/8 vgma 5 + (vgma 4 ? vgma 5 ) 3/8 vgma 5 + (vgma 4 ? vgma 5 ) 2/8 vgma 5 + (vgma 4 ? vgma 5 ) 1/8 vgma 5 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vh24 vh25 vh2 6 vh27 vh2 8 vh2 9 vh 30 vh31 vgma 6 + (vgma 5 ? vgma 6 ) 7/8 vgma 6 + (vgma 5 ? vgma 6 ) 6/8 vgma 6 + (vgma 5 ? vgma 6 ) 5/8 vgma 6 + (vgma 5 ? vgma 6 ) 4/8 vgma 6 + (vgma 5 ? vgma 6 ) 3/8 vgma 6 + (vgma 5 ? vgma 6 ) 2/8 vgma 6 + (vgma 5 ? vgma 6 ) 1/8 vgma 6 note: vdd2 3 vgma1>vgma2>vgma3>vgma4>vgma5>vgma6>vgma7>vgma8>vgma9>vgma10>vgma11 3 vss2
6 bit 300 / 309 channel tft-lcd source driver S6C0641 11 table 2. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vh 32 vh33 vh34 vh 35 vh36 vh 37 vh 38 vh39 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vh 40 vh41 vh 42 vh 43 vh44 vh 45 vh 46 vh47 vgma 8 + (vgma 7 ? vgma 8 ) 7/8 vgma 8 + (vgma 7 ? vgma 8 ) 6/8 vgma 8 + (vgma 7 ? vgma 8 ) 5/8 vgma 8 + (vgma 7 ? vgma 8 ) 4/8 vgma 8 + (vgma 7 ? vgma 8 ) 3/8 vgma 8 + (vgma 7 ? vgma 8 ) 2/8 vgma 8 + (vgma 7 ? vgma 8 ) 1/8 vgma 8 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vh 48 vh49 vh 50 vh 51 vh52 vh53 vh54 vh55 vgma 9 + (vgma 8 ? vgma 9 ) 7/8 vgma 9 + (vgma 8 ? vgma 9 ) 6/8 vgma 9 + (vgma 8 ? vgma 9 ) 5/8 vgma 9 + (vgma 8 ? vgma 9 ) 4/8 vgma 9 + (vgma 8 ? vgma 9 ) 3/8 vgma 9 + (vgma 8 ? vgma 9 ) 2/8 vgma 9 + (vgma 8 ? vgma 9 ) 1/8 vgma 9 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vh56 vh57 vh58 vh59 vh60 vh61 vh 62 vh63 vgma 10 + (vgma 9 ? vgma 10 ) 6/7 vgma 10 + (vgma 9 ? vgma 10 ) 5/7 vgma 10 + (vgma 9 ? vgma 10 ) 4/7 vgma 10 + (vgma 9 ? vgma 10 ) 3/7 vgma 10 + (vgma 9 ? vgma 10 ) 2/7 vgma 10 + (vgma 9 ? vgma 10 ) 1/7 vgma 10 vgma 11 rgma (gamma-corrected resistance) ratio. (if the rgma1 equals 1) rgma1 1.00 rgma6 0.84 rgma2 2.00 rgma7 0.66 rgma3 2.77 rgma8 0.84 rgma4 1.50 rgma9 1.42 rgma5 0.90 rgma10 1.05 rgma1 = 2.31 k w
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 12 table 3. relationship between input data and output voltage value: in case of using 10 levels of gamma-corrected power supplies (vgma1 = open) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vh0 vh1 vh2 vh 3 vh4 vh 5 vh 6 vh7 vgma 2 vgma 3 + (vgma2 ? vgma 3 ) 6/7 vgma 3 + (vgma2 ? vgma 3 ) 5/7 vgma 3 + (vgma2 ? vgma 3 ) 4/7 vgma 3 + (vgma2 ? vgma 3 ) 3/7 vgma 3 + (vgma2 ? vgma 3 ) 2/7 vgma 3 + (vgma2 ? vgma 3 ) 1/7 vgma 3 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vh 8 vh9 vh 1 0 vh 1 1 vh12 vh 13 vh 1 4 vh15 vgma 4 + (vgma 3 ? vgma 4 ) 7/8 vgma 4 + (vgma 3 ? vgma 4 ) 6/8 vgma 4 + (vgma 3 ? vgma 4 ) 5/8 vgma 4 + (vgma 3 ? vgma 4 ) 4/8 vgma 4 + (vgma 3 ? vgma 4 ) 3/8 vgma 4 + (vgma 3 ? vgma 4 ) 2/8 vgma 4 + (vgma 3 ? vgma 4 ) 1/8 vgma 4 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vh 16 vh17 vh 18 vh 19 vh20 vh2 1 vh2 2 vh23 vgma 5 + (vgma 4 ? vgma 5 ) 7/8 vgma 5 + (vgma 4 ? vgma 5 ) 6/8 vgma 5 + (vgma 4 ? vgma 5 ) 5/8 vgma 5 + (vgma 4 ? vgma 5 ) 4/8 vgma 5 + (vgma 4 ? vgma 5 ) 3/8 vgma 5 + (vgma 4 ? vgma 5 ) 2/8 vgma 5 + (vgma 4 ? vgma 5 ) 1/8 vgma 5 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vh24 vh25 vh2 6 vh27 vh2 8 vh2 9 vh 30 vh31 vgma 6 + (vgma 5 ? vgma 6 ) 7/8 vgma 6 + (vgma 5 ? vgma 6 ) 6/8 vgma 6 + (vgma 5 ? vgma 6 ) 5/8 vgma 6 + (vgma 5 ? vgma 6 ) 4/8 vgma 6 + (vgma 5 ? vgma 6 ) 3/8 vgma 6 + (vgma 5 ? vgma 6 ) 2/8 vgma 6 + (vgma 5 ? vgma 6 ) 1/8 vgma 6 note: vdd2 3 vgma1>vgma2>vgma3>vgma4>vgma5>vgma6>vgma7>vgma8>vgma9>vgma10>vgma11 3 vss2
6 bit 300 / 309 channel tft-lcd source driver S6C0641 13 table 3. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vh 32 vh33 vh34 vh 35 vh36 vh 37 vh 38 vh39 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vh 40 vh41 vh 42 vh 43 vh44 vh 45 vh 46 vh47 vgma 8 + (vgma 7 ? vgma 8 ) 7/8 vgma 8 + (vgma 7 ? vgma 8 ) 6/8 vgma 8 + (vgma 7 ? vgma 8 ) 5/8 vgma 8 + (vgma 7 ? vgma 8 ) 4/8 vgma 8 + (vgma 7 ? vgma 8 ) 3/8 vgma 8 + (vgma 7 ? vgma 8 ) 2/8 vgma 8 + (vgma 7 ? vgma 8 ) 1/8 vgma 8 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vh 48 vh49 vh 50 vh 51 vh52 vh53 vh54 vh55 vgma 9 + (vgma 8 ? vgma 9 ) 7/8 vgma 9 + (vgma 8 ? vgma 9 ) 6/8 vgma 9 + (vgma 8 ? vgma 9 ) 5/8 vgma 9 + (vgma 8 ? vgma 9 ) 4/8 vgma 9 + (vgma 8 ? vgma 9 ) 3/8 vgma 9 + (vgma 8 ? vgma 9 ) 2/8 vgma 9 + (vgma 8 ? vgma 9 ) 1/8 vgma 9 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vh56 vh57 vh58 vh59 vh60 vh61 vh 62 vh63 vgma 10 + (vgma 9 ? vgma 10 ) 6/7 vgma 10 + (vgma 9 ? vgma 10 ) 5/7 vgma 10 + (vgma 9 ? vgma 10 ) 4/7 vgma 10 + (vgma 9 ? vgma 10 ) 3/7 vgma 10 + (vgma 9 ? vgma 10 ) 2/7 vgma 10 + (vgma 9 ? vgma 10 ) 1/7 vgma 10 vgma 11 rgma (gamma-corrected resistance) ratio. (if the rgma2 equals 1) rgma1 - rgma6 0.42 rgma2 1.00 rgma7 0.33 rgma3 1.39 rgma8 0.42 rgma4 0.75 rgma9 0.71 rgma5 0.45 rgma10 0.53 rgma1 = 4.62 k w
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 14 table 4. relationship between input data and output voltage value: in case of using 10 levels of gamma-corrected power supplies (vgma2 = open) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vh0 vh1 vh2 vh 3 vh4 vh 5 vh 6 vh7 vgma 3 + (vgma2 ? vgma 3 ) 7/8 vgma 3 + (vgma2 ? vgma 3 ) 6/8 vgma 3 + (vgma2 ? vgma 3 ) 5/8 vgma 3 + (vgma2 ? vgma 3 ) 4/8 vgma 3 + (vgma2 ? vgma 3 ) 3/8 vgma 3 + (vgma2 ? vgma 3 ) 2/8 vgma 3 + (vgma2 ? vgma 3 ) 1/8 vgma 3 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vh 8 vh9 vh 1 0 vh 1 1 vh12 vh 13 vh 1 4 vh15 vgma 4 + (vgma 3 ? vgma 4 ) 7/8 vgma 4 + (vgma 3 ? vgma 4 ) 6/8 vgma 4 + (vgma 3 ? vgma 4 ) 5/8 vgma 4 + (vgma 3 ? vgma 4 ) 4/8 vgma 4 + (vgma 3 ? vgma 4 ) 3/8 vgma 4 + (vgma 3 ? vgma 4 ) 2/8 vgma 4 + (vgma 3 ? vgma 4 ) 1/8 vgma 4 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vh 16 vh17 vh 18 vh 19 vh20 vh2 1 vh2 2 vh23 vgma 5 + (vgma 4 ? vgma 5 ) 7/8 vgma 5 + (vgma 4 ? vgma 5 ) 6/8 vgma 5 + (vgma 4 ? vgma 5 ) 5/8 vgma 5 + (vgma 4 ? vgma 5 ) 4/8 vgma 5 + (vgma 4 ? vgma 5 ) 3/8 vgma 5 + (vgma 4 ? vgma 5 ) 2/8 vgma 5 + (vgma 4 ? vgma 5 ) 1/8 vgma 5 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vh24 vh25 vh2 6 vh27 vh2 8 vh2 9 vh 30 vh31 vgma 6 + (vgma 5 ? vgma 6 ) 7/8 vgma 6 + (vgma 5 ? vgma 6 ) 6/8 vgma 6 + (vgma 5 ? vgma 6 ) 5/8 vgma 6 + (vgma 5 ? vgma 6 ) 4/8 vgma 6 + (vgma 5 ? vgma 6 ) 3/8 vgma 6 + (vgma 5 ? vgma 6 ) 2/8 vgma 6 + (vgma 5 ? vgma 6 ) 1/8 vgma 6 note: vdd2 3 vgma1>vgma2>vgma3>vgma4>vgma5>vgma6>vgma7>vgma8>vgma9>vgma10>vgma11 3 vss2
6 bit 300 / 309 channel tft-lcd source driver S6C0641 15 table 4. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vh 32 vh33 vh34 vh 35 vh36 vh 37 vh 38 vh39 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vh 40 vh41 vh 42 vh 43 vh44 vh 45 vh 46 vh47 vgma 8 + (vgma 7 ? vgma 8 ) 7/8 vgma 8 + (vgma 7 ? vgma 8 ) 6/8 vgma 8 + (vgma 7 ? vgma 8 ) 5/8 vgma 8 + (vgma 7 ? vgma 8 ) 4/8 vgma 8 + (vgma 7 ? vgma 8 ) 3/8 vgma 8 + (vgma 7 ? vgma 8 ) 2/8 vgma 8 + (vgma 7 ? vgma 8 ) 1/8 vgma 8 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vh 48 vh49 vh 50 vh 51 vh52 vh53 vh54 vh55 vgma 9 + (vgma 8 ? vgma 9 ) 7/8 vgma 9 + (vgma 8 ? vgma 9 ) 6/8 vgma 9 + (vgma 8 ? vgma 9 ) 5/8 vgma 9 + (vgma 8 ? vgma 9 ) 4/8 vgma 9 + (vgma 8 ? vgma 9 ) 3/8 vgma 9 + (vgma 8 ? vgma 9 ) 2/8 vgma 9 + (vgma 8 ? vgma 9 ) 1/8 vgma 9 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vh56 vh57 vh58 vh59 vh60 vh61 vh 62 vh63 vgma 10 + (vgma 9 ? vgma 10 ) 6/7 vgma 10 + (vgma 9 ? vgma 10 ) 5/7 vgma 10 + (vgma 9 ? vgma 10 ) 4/7 vgma 10 + (vgma 9 ? vgma 10 ) 3/7 vgma 10 + (vgma 9 ? vgma 10 ) 2/7 vgma 10 + (vgma 9 ? vgma 10 ) 1/7 vgma 10 vgma 11 rgma (gamma-corrected resistance) ratio. (if the sum of rgma1 and rgma2 equals 1) rgma1 rgma6 0.37 rgma2 1.00 rgma7 0.29 rgma3 1.21 rgma8 0.37 rgma4 0.66 rgma9 0.62 rgma5 0.39 rgma10 0.46 rgma1 + rgma2 = 5.28 k w
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 16 table 5. relationship between input data and output voltage value: in case of using 9 levels of gamma-corrected power supplies (vgma2, vgma10 = open) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00h 01h 02h 03 h 04h 05 h 06 h 07h 0 0 0 1 1 1 vh0 vh1 vh2 vh 3 vh4 vh 5 vh 6 vh7 vgma 3 + (vgma2 ? vgma 3 ) 7/8 vgma 3 + (vgma2 ? vgma 3 ) 6/8 vgma 3 + (vgma2 ? vgma 3 ) 5/8 vgma 3 + (vgma2 ? vgma 3 ) 4/8 vgma 3 + (vgma2 ? vgma 3 ) 3/8 vgma 3 + (vgma2 ? vgma 3 ) 2/8 vgma 3 + (vgma2 ? vgma 3 ) 1/8 vgma 3 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 08 h 09h 0a h 0b h 0ch 0d h 0e h 0fh 0 0 1 1 1 1 vh 8 vh9 vh 1 0 vh 1 1 vh12 vh 13 vh 1 4 vh15 vgma 4 + (vgma 3 ? vgma 4 ) 7/8 vgma 4 + (vgma 3 ? vgma 4 ) 6/8 vgma 4 + (vgma 3 ? vgma 4 ) 5/8 vgma 4 + (vgma 3 ? vgma 4 ) 4/8 vgma 4 + (vgma 3 ? vgma 4 ) 3/8 vgma 4 + (vgma 3 ? vgma 4 ) 2/8 vgma 4 + (vgma 3 ? vgma 4 ) 1/8 vgma 4 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 10 h 11h 12 h 13 h 14h 15 h 16 h 17h 0 1 0 1 1 1 vh 16 vh17 vh 18 vh 19 vh20 vh2 1 vh2 2 vh23 vgma 5 + (vgma 4 ? vgma 5 ) 7/8 vgma 5 + (vgma 4 ? vgma 5 ) 6/8 vgma 5 + (vgma 4 ? vgma 5 ) 5/8 vgma 5 + (vgma 4 ? vgma 5 ) 4/8 vgma 5 + (vgma 4 ? vgma 5 ) 3/8 vgma 5 + (vgma 4 ? vgma 5 ) 2/8 vgma 5 + (vgma 4 ? vgma 5 ) 1/8 vgma 5 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 18 h 19h 1a h 1bh 1c h 1d h 1e h 1fh 0 1 1 1 1 1 vh24 vh25 vh2 6 vh27 vh2 8 vh2 9 vh 30 vh31 vgma 6 + (vgma 5 ? vgma 6 ) 7/8 vgma 6 + (vgma 5 ? vgma 6 ) 6/8 vgma 6 + (vgma 5 ? vgma 6 ) 5/8 vgma 6 + (vgma 5 ? vgma 6 ) 4/8 vgma 6 + (vgma 5 ? vgma 6 ) 3/8 vgma 6 + (vgma 5 ? vgma 6 ) 2/8 vgma 6 + (vgma 5 ? vgma 6 ) 1/8 vgma 6 note: vdd2 3 vgma1>vgma2>vgma3>vgma4>vgma5>vgma6>vgma7>vgma8>vgma9>vgma10>vgma11 3 vss2
6 bit 300 / 309 channel tft-lcd source driver S6C0641 17 table 5. relationship between input data and output voltage value (continued) input data dx5 dx4 dx3 dx2 dx1 dx0 g/s output voltage 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 2 0h 21h 22h 23 h 24h 25 h 26 h 27h 1 0 0 1 1 1 vh 32 vh33 vh34 vh 35 vh36 vh 37 vh 38 vh39 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 + (vgma 6 ? vgma 7 ) 7/8 vgma 7 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 28 h 29h 2a h 2b h 2ch 2d h 2e h 2fh 1 0 1 1 1 1 vh 40 vh41 vh 42 vh 43 vh44 vh 45 vh 46 vh47 vgma 8 + (vgma 7 ? vgma 8 ) 7/8 vgma 8 + (vgma 7 ? vgma 8 ) 6/8 vgma 8 + (vgma 7 ? vgma 8 ) 5/8 vgma 8 + (vgma 7 ? vgma 8 ) 4/8 vgma 8 + (vgma 7 ? vgma 8 ) 3/8 vgma 8 + (vgma 7 ? vgma 8 ) 2/8 vgma 8 + (vgma 7 ? vgma 8 ) 1/8 vgma 8 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 30 h 31h 32 h 33 h 34h 35 h 36 h 37h 1 1 0 1 1 1 vh 48 vh49 vh 50 vh 51 vh52 vh53 vh54 vh55 vgma 9 + (vgma 8 ? vgma 9 ) 7/8 vgma 9 + (vgma 8 ? vgma 9 ) 6/8 vgma 9 + (vgma 8 ? vgma 9 ) 5/8 vgma 9 + (vgma 8 ? vgma 9 ) 4/8 vgma 9 + (vgma 8 ? vgma 9 ) 3/8 vgma 9 + (vgma 8 ? vgma 9 ) 2/8 vgma 9 + (vgma 8 ? vgma 9 ) 1/8 vgma 9 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 38 h 39h 3a h 3bh 3c h 3d h 3e h 3fh 1 1 1 1 1 1 vh56 vh57 vh58 vh59 vh60 vh61 vh 62 vh63 vgma 11 + (vgma 9 ? vgma11) 7/8 vgma 11 + (vgma 9 ? vgma11) 6/8 vgma11 + (vgma 9 ? vgma11) 5/8 vgma11 + (vgma 9 ? vgma11) 4/8 vgma11 + (vgma 9 ? vgma11) 3/8 vgma11 + (vgma 9 ? vgma11) 2/8 vgma11 + (vgma 9 ? vgma11) 1/8 vgma 11 rgma (gamma-corrected resistance) ratio. (if the sum of rgma1 and rgma2 equals 1) rgma1 rgma6 0.37 rgma2 1.00 rgma7 0.29 rgma3 1.21 rgma8 0.37 rgma4 0.66 rgma9 rgma5 0.39 rgma10 0.71 rgma1 + rgma2 = 5.28 k w
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 18 absolute maximum ratings t able 6. absolute maximum ratings (vss1 = vss2 = 0 v) parameter symbol ratings unit logic supply voltage vdd1 -0.3 to 6.5 driver supply voltage vdd2 -0.3 to 6.5 vgma1 - 10 -0.3 to vdd2 + 0.3 input voltage others -0.3 to vdd1 + 0.3 dio1, 2 -0.3 to vdd1 + 0.3 output voltage y1 - y 309 -0.3 to vdd2 + 0.3 v operation temperature top r -20 to 75 storage temperature tstg -55 to 1 25 c cautions: if lsis are stressed beyond those listed above ? absolute maximum ratings ? , they may be permanently destroyed. these are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. turn on power order: vdd1 ? control signal input ? vdd2 ? vgma1 - vgma11 turn off power order: vgma1 - vgma11 ? vdd2 ? control signal input ? vdd1 recommended operation condition s table 7. recommended operation conditions ( ta = -20 to 75 c , vss1 = vss2 = 0 v) parameter symbol min. typ. max. unit logic supply voltage vdd1 3.0 3. 3 5.5 v driver supply voltage vdd2 3.0 5 .0 5.5 v gamma corrected voltage vgma1 ? vgma11 vss2 - vdd2 v maximum clock frequency fmax vdd1 = 3.3 v 55 mhz output load capacitance cl - - 150 pf / pin
6 bit 300 / 309 channel tft-lcd source driver S6C0641 19 dc characteristics table 8. dc characteristics (ta = -20 to 75 c, vdd1 = 3.0 to 5.5 v, vdd2 = 3.0 to 5.5 v, vss1 = vss2 = 0 v ) parameter symbol condition min. typ. max. unit high level input voltage vih 0.7 vdd1 - vdd1 low level input voltage vil 0 - 0. 3 vdd1 v input leakage current il shl, clk2, d00 ? d 25 , clk1, dio1 (dio2) -0.5 - 0.5 m a high level output voltage voh dio1 (dio2), vdd1=3.3v io = - 1 .0 ma vdd1 - 0. 5 - - low level output voltage vol dio1 (dio2), vdd1=3.3v io = + 1 .0 ma - - 0. 5 v resistor r0 - r 62 rn 0.7 rn 1.3 w ivoh vdd2 = 5 .0 v, vx = 3 .5 v, vyo = 4 .5 v - -1.5 -0.5 ma driver output current ivol vdd2 = 5 .0 v, vx = 1 .5 v, vyo = 0 .5 v 0.5 0.5 - ma output voltage deviation d vo vss2 + 0. 2 v to vdd2 - 1.5 v - 10 20 mv output voltage range vyo input data: 00h to 3 fh vss2 + 0. 2 - vdd2 - 0. 2 v logic part dynamic current idd1 vdd1 = 3.0 v ( 2 ) - 3.5 5.5 ma driver part dynamic current idd2 vdd 1 = 3.0 v, vdd2 = 5.0 v , vgma1 = 4.5 v, vgma11 = 0.5 v - 5.5 7 .0 notes: 1. vyo is the output voltage of analog output pins y1 to y309. vx is the voltage applied to analog output pins y1 to y309. 2. clk1 period is defined to be 30 m s at fclk2 = 30 mhz, data pattern = 101010 , (checkerboard pattern), ta = 25 c
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 20 ac characteristics table 9. ac characteristics (ta = -20 to 75 c, v dd2 = 3.0 to 5.5 v, vdd1 = 3.0 to 5.5 v, v ss1 = vss2 = 0 v) p arameter s ymbol c ondition min. typ. m ax . u nit clock pulse width pwclk - 1 8 - - clock pulse low period pwclk(l) - 4 - - clock pulse high period pwclk(h) - 4 - - data setup time tsetup1 (1) 4 - - data hold time thold1 (1) 0 - - start pulse setup time tsetup2 (1) 4 - - start pulse hold time thold2 (1) 0 - - start pulse delay time tplh1 vdd1 = 3.3 v cl = 35 pf - - 1 4 ns clk1 setup time tsetup3 - 1 - - clk2 period driver output delay time1 tphl1 (2) - - 3 driver output delay time2 tphl2 (3) - - 10 m s clk1 pulse high period pwclk1 - 2 - - clk2 period data invalid period tinv dio1 (2) - ? clk2 - 1 clk2 period last data timing tldt - 0 - - ns clk1-clk2 time tclk1 ? clk2 clk1 - ? clk2 - 6 - - ns notes: 1. input condition (vih = 0.7 vdd1, vil = 0.3 vdd1) 2. the value is specified when the drive voltage value reaches the target output voltage level of 90% 3. the value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
6 bit 300 / 309 channel tft-lcd source driver S6C0641 21 waveforms clk2 tldt 0.5vdd1 invalid data last data clk1 dxx tclk1-clk2 tsetup1 pwclk(h) invalid data clk2 dio1 input (dio2 input) clk1 y(1:309) 1st last-1 last pwclk(l) vih vil thold1 tplh1 target output voltage 90% target output voltage dxx pwclk tsetup2 1st data thold2 dio2 output (dio1 output) tsetup3 pwclk1 tphl2 tinv tphl1 tsetup1 thold1 clk2 clk1 figure 5. waveforms
S6C0641 6 bit 300 / 309 channel tft-lcd source driver 22 relationships between clk1, start pulse (dio1, dio2) and blanking period invalid data clk2 dio1 input (dio2 input) clk1 dxx 1st data 1clk2(min.) nth data n-1th data 2nd data blanking time = min. 3clk2 last data first data in the next line 0.5vdd1 1clk2 1clk2(max.) clk2 clk1 y (1:309) hold analog output hi-z figure 6. waveforms

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